The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, a semiconductor device employing a strained-Si layer as an active region and a method of manufacturing the same.
The performance of Si semiconductor elements, in particular, MOSFETs, has increased year after year with the advance of large-scale integrated circuits (LSI). However, it has been recently pointed out that the miniaturization attained by a lithographic technology has reached its limit, and that a carrier mobility has almost reached theoretical mobility in Si. Under the circumstances, it is difficult to further improve the performance of MOSFETs.
To attain higher performance of the semiconductor device, attempts have been made to use a crystal such as a GaAs semiconductor crystal or an SiC semiconductor crystal in place of an Si crystal since they have a faster theoretical mobility than the Si crystal.
However, it is difficult to introduce the manufacturing process for the GaAs semiconductor crystal or the SiC crystal into the manufacturing process of the Si device presently used. Therefore, a lot of time and labor are required for developing this kind of device. As a matter of fact, when this kind of device is manufactured on a large scale, the whole manufacturing line must be redesigned from the beginning or some of the manufacturing apparatus must be replaced.
Therefore, it is now strongly desired that a high-performance Si-based semiconductor device is developed in a short development period and at a low cost by using know-how of the presently-used manufacturing process and manufacturing apparatus for the Si device.
To attain such a device, studies have been made to improve the performance of Si-MOSFET by increasing the electron mobility in Si. AS one of the methods for increasing the electron mobility in Si, a technique for applying a strain to a Si layer has drawn attention. Generally, when the strain is applied to a semiconductor layer, the band structure is changed to suppress the scattering of carriers in a channel. Therefore, the electron mobility is expected to improve.
To explain more specifically, when a compound crystal layer including a material having a lattice constant larger than that of Si is formed on a Si substrate, for example, a SiGe compound crystal containing 20 atomic % of Ge (hereinafter, simply referred to as “SiGe layer”) is formed as thick as several μm so as to obtain lattice relaxation, and then, a Si layer as thin as several nm is formed on the lattice-relaxed SiGe layer thus obtained, strain, which is generated due to the difference in lattice constant between SiGe and Si, is applied to the Si layer. As a result, a strained Si layer is obtained.
It has been reported that if the strained Si layer thus obtained is employed as a channel of a MOSFET, the electron mobility can be greatly improved to about 1.76 times larger than that of the non-strained Si layer (J. Welser, J. L. Hoyl, S. Tagkagi and J. F. Gibbons, IEDM 94-373).
Furthermore, another method is known for improving the electron mobility in Si by reducing the channel length of the MOSFET. However, when the channel length is reduced, the effect of stray capacitance increases, with the result that it is difficult to improve the electron mobility as desired.
To overcome this problem, attention is drawn to a structure having a channel layer formed within an SOI layer (Silicon On Insulator: an Si layer is formed on an Si substrate with an insulating film interposed between them). Since the channel layer is completely isolated by the insulating film in this structure, it becomes easier to decrease the stray capacitance and isolate the element. Furthermore, reduction of power consumption and higher integration can be expected.
Under the circumstances, attempts have been made to form a structure of a semiconductor device by employing the strained Si layer (for improving the electron mobility) in the SOI structure (responsible for lowering the stray capacitance and attaining element isolation).
The structure of such a semiconductor device will be explained with reference to FIGS. 1A and 1B.
As shown in FIG. 1A, an SOI substrate having an SiO2 insulating film 2 and SOI layer 3 having a thickness between 20 nm and 30 nm previously formed on an Si substrate 1 is prepared. Thereafter, an SiGe layer 4 containing 20 atomic % of Ge and having a larger lattice constant than Si is formed on the SOI substrate. The SiGe layer herein is formed sufficiently thicker than the SOI layer 3.
Then, as shown in FIG. 1B, annealing is performed for one hour at 1100° C. in a nitrogen containing atmosphere. At this time, since tensile strain is applied from the SiGe layer 4 to the SOI layer 3, the SOI layer 3 is plastically deformed and thus lattice-relaxed. At the same time, the SOI layer 4 is also lattice-relaxed. By the plastic deformation, a dislocation 33 such as a threading dislocation and a misfit dislocation, is produced in the SOI layer 3.
Subsequently, a thin Si film is formed on the lattice-relaxed SiGe layer 4. Due to the presence of the thin Si film, it is possible to form a strained Si layer 5 having a tensile strain.
Since the dislocation is produced and confined within the lattice-relaxed SOI layer 3, it has been considered that the most of dislocation 33 is not propagated to the lattice-relaxed SiGe layer 4. However, it was found that if annealing for lattice relaxation is performed in a nitrogen-containing atmosphere for one hour at a temperature of 1100° C., the dislocation 33 can be propagated to the surface of SiGe layer 4 with a density of about one/10 μm2. Due to defects such as a dislocation, the crystallinity of the strained Si layer 5 deteriorates. Thereafter, a semiconductor device such as a MOSFET is formed on the strained Si layer 5. However, the deterioration in crystallinity of the strained Si layer 5 may degrade characteristics of the resultant semiconductor device. The deterioration more significantly appears with the miniaturization of the semiconductor device.
The defects produced by lattice-relaxation of the SiGe layer 4 may be sometimes amplified in a high-temperature processing step when a gate and an electrode are formed and when annealing is performed for recovering the crystallinity after ion doping. In this case, the crystallinity of the strained Si layer 5 may be further degraded.
To prevent the dislocation 33, which is produced in the SOI layer for lattice-relaxation, from propagating to the surface of the SiGe layer, the SiGe layer 4 must be formed with a thickness of several μm or more. However, to produce a sufficient effect of suppressing the stray capacitance due to the SOI substrate structure, it is necessary to suppress a total thickness from the SiO2 insulating layer 2 to the strained Si layer 5 (serving as a channel layer) as much as possible. However, since, in this method, the SiGe layer 4 must be formed with several μm, it is impossible to sufficiently produce the effect brought about by the SOI substrate structure.
As described above, there are problems in a conventional semiconductor device having a strained Si layer (as a channel layer) formed on the SOI substrate. That is, to prevent the defects, the semiconductor film has to be formed thick on the SOI substrate insulating film. If the thickness of the semiconductor layer formed on the SOI substrate insulting film is reduced, the defects become clearly apparent.